Semiconductor device comprising a half-bridge circuit The invention relates to a semiconductor device comprising a half-bridge circuit with two n-channel DMOS transistors forming a series connection between a terminal V.sub.SS for a low voltage and a terminal V.sub.dd for a high voltage, which semiconductor device also comprises a semiconductor body with a p-type substrate and, provided on said substrate, an epitaxial layer in which, for the transistors, two separate regions are defined which are surrounded within the semiconductor body by two electrically insulated cup-shaped n-type zones which each have a bottom formed by a buried n-type zone at the interface between the substrate and the epitaxial layer, and a raised wall formed by an n-type zone which extends from the surface across the thickness of the epitaxial layer to the underlying buried zone, each of the transistors comprising an n-type source and drain zone, the source zone of each transistor being located in a p-type backgate region, and, of one of the transistors, hereinafter referred to as first transistor, the source zone being connected to V.sub.ss and the drain zone being connected to the source zone of the second transistor whose drain zone is connected to V.sub.dd. Such a device, which can be used, for example, in an electronic ballast for gas-discharge lamps or in driver circuits for motors is known, inter alia, from the article "A versatile 250/300-V IC process for analog and switching applications" A. W. Ludikhuize, published in IEEE Transactions on Electron Devices, Vol. ED-33, No. 12, December 1986, pp. 2008/2015. The use of two half bridges enables the circuit to be readily extended to a full bridge circuit. The use of DMOS transistors has various advantages which are known per se, such as sturdiness, which makes the transistor resistant to high voltages and/or high powers. In addition, this type of transistor can very suitably be used in the case of inductive loads as a result of which the voltage at the output may be higher than V.sub.dd and lower than V.sub.ss, as the electric charge can be efficiently removed via the body diode of the DMOS.
In the known device, an n-type epitaxial layer is used in which islands are formed in known manner by means of a deep p-type diffusion, which islands accommodate the transistors; see, in particular, FIG. 14 and FIG. 15 of said publication. The half bridge is constructed symmetrically, that is, the construction of the transistors is identical. As a result, the n-type cup-shaped zone is connected, both in the first transistor (also referred to as low-side transistor) and in the second transistor (also referred to as high-side transistor), to the drain. In the case of the high-side transistor, this will generally not be problematic. In the low-side transistor, however, the drain, and hence the n-type cup-shaped zone, is coupled to the output of the (half) bridge and thus its potential varies. In the case of an inductive load, the voltage at the output, that is the node of the drain of the first transistor and the source of the second transistor, may be reduced to a level which is lower than the substrate voltage, so that the pn-junction between the substrate and the n-type cup-shaped zone of the first transistor becomes forward-poled and electrons are injected into the substrate. This may cause disturbances in other circuit elements or latch-up. In addition, so-called dV/dt effects may occur, which, in the case of a rapid increase of the potential on the output, also cause a local increase of the potential in the, generally rather high-ohmic, substrate, so that one may observe the occurrence of disturbances and latch-up with neighboring n-type zones at, for example 0 V.